Open-Source 256-bit HTML Computer

Program Editor (Assembly-like)

Speed (ms/step)

CPU State

PC

0

Flags

Z=0 N=0 C=0

Status

Ready

Registers (hex)

Reg	Hex (64 nybbles)

Watch Memory (addresses are word-indexed)

Address

Value

0x0

I/O Console

Architecture & Instruction Set

Word Size

256-bit unsigned (mod 2^256 arithmetic)

Registers

R0..R7 (general purpose)

Flags

Z (zero), N (sign bit), C (carry on add/sub)

Memory

4096 words (256-bit), addressed by word index

Assembler

Comments start with ; or # · Labels end with : · Hex immediates with 0x · Decimal otherwise.

Ops

LI Rn, imm · Load immediate

MOVE Rd, Rs

LOAD Rd, [Ra+off] · off optional

STORE Rs, [Ra+off]

ADD|SUB|MUL|DIV|AND|OR|XOR Rd, Ra, Rb

NOT Rd, Ra

SHL|SHR Rd, Ra, imm

CMP Ra, Rb · sets Z,N

JMP label | JZ label | JNZ label

OUT Rs · low 8-bit as char · OUTN Rs · print decimal

IN Rd · prompt for decimal · HALT

Hackable VM Core (edit & Apply)

// You can customize the CPU below. Keep the same API shape.
vmCore = {
  MASK: (1n << 256n) - 1n,
  U256(x){ return (x & this.MASK); },
  toU256(x){ return (BigInt(x) & this.MASK); },
  add(a,b){ const s = a + b; return [this.U256(s), s > this.MASK ? 1 : 0]; },
  sub(a,b){ const s = a - b; return [this.U256(s), s < 0n ? 1 : 0]; },
  mul(a,b){ const s = a * b; return [this.U256(s), 0]; },
  div(a,b){ return [b===0n?0n:a/b, 0]; },
  shl(a,n){ return this.U256(a << BigInt(n)); },
  shr(a,n){ return this.U256(a >> BigInt(n)); },
  setZN(vm, v){ vm.Z = (v === 0n)?1:0; vm.N = (v >> 255n) & 1n ? 1:0; },
  step(vm){
    if (vm.PC < 0 || vm.PC >= vm.prog.length) { vm.halted = true; return; }
    const ins = vm.prog[vm.PC];
    const op = ins.op;
    const R = (i)=>vm.reg[i|0];
    const W = (i,v)=>{ vm.reg[i|0]=this.U256(v); };
    const memMask = vm.mem.length;
    const addr = (base, off=0n)=> Number((base + off) % BigInt(memMask));

switch(op){
      case 'LI':   W(ins.a, BigInt(ins.im)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'MOVE': W(ins.a, R(ins.b)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'LOAD': W(ins.a, vm.mem[addr(R(ins.b), BigInt(ins.off||0))]); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'STORE': vm.mem[addr(R(ins.b), BigInt(ins.off||0))] = this.U256(R(ins.a)); vm.PC++; break;
      case 'ADD': { const [v,c]=this.add(R(ins.a), R(ins.b)); W(ins.a, v); vm.C=c; this.setZN(vm,v); vm.PC++; break; }
      case 'SUB': { const [v,c]=this.sub(R(ins.a), R(ins.b)); W(ins.a, v); vm.C=c; this.setZN(vm,v); vm.PC++; break; }
      case 'MUL': { const [v,c]=this.mul(R(ins.a), R(ins.b)); W(ins.a, v); vm.C=c; this.setZN(vm,v); vm.PC++; break; }
      case 'DIV': { const [v,c]=this.div(R(ins.a), R(ins.b)); W(ins.a, v); vm.C=c; this.setZN(vm,v); vm.PC++; break; }
      case 'AND': W(ins.a, R(ins.a) & R(ins.b)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'OR':  W(ins.a, R(ins.a) | R(ins.b)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'XOR': W(ins.a, R(ins.a) ^ R(ins.b)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'NOT': W(ins.a, ~R(ins.b)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'SHL': W(ins.a, this.shl(R(ins.a), ins.im)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'SHR': W(ins.a, this.shr(R(ins.a), ins.im)); this.setZN(vm, R(ins.a)); vm.PC++; break;
      case 'CMP': { const v = this.U256((R(ins.a) - R(ins.b))); vm.Z = (v===0n)?1:0; vm.N = ((R(ins.a) >> 255n)&1n) ? 1:0; vm.PC++; break; }
      case 'JMP': vm.PC = ins.t; break;
      case 'JZ':  vm.PC = (vm.Z? ins.t : vm.PC+1); break;
      case 'JNZ': vm.PC = (!vm.Z? ins.t : vm.PC+1); break;
      case 'OUT': vm.outChar(Number(R(ins.a) & 0xffn)); vm.PC++; break;
      case 'OUTN': vm.outNum(R(ins.a)); vm.PC++; break;
      case 'IN':  vm.readNum().then(v=>{ vm.reg[ins.a]=this.U256(v); vm.PC++; }); return; // async step
      case 'HALT': vm.halted = true; break;
      default: vm.halted = true; vm.error = `Unknown op ${op}`;
    }
  }
};